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CS4270 24-Bit, 192 kHz Stereo Audio CODEC
D/A Features
High Performance - 105 dB Dynamic Range - -95 dB THD+N Selectable Serial Audio Interface Formats - Left-Justified up to 24-bit - IS up to 24-bit - Right-Justified 16-, and 24-Bit Control Output for External Muting On-Chip Digital De-Emphasis Popguard Technology Multi-bit Conversion Digital Volume Control
A/D Features
High Performance - 105 dB Dynamic Range - -95 dB THD+N Multi-bit Delta Sigma Conversion High-Pass Filter to remove DC Offsets Selectable Serial Audio Interface Formats - Left-Justified up to 24-bit - IS up to 24-bit
System Features
Direct Interface with Logic Levels 1.8 V to 5 V Internal Digital Loopback Stand-Alone or Control Port Functionality Single-Ended Analog Architecture Supports all Audio Sample Rates from 4 kHz to 216 kHz
Control Port Supply 1.8 V to 5 V
Digital Supply 3.3 V to 5 V
Analog Supply 3.3 V to 5 V
Level Translator
Hardware Mode or I2C/SPI Software Mode Control Data
Register/Hardware Configuration
Internal Voltage Reference
Reset
External Mute Control
2
Mute Signals
PCM Serial Audio Input Serial Interface
2
Volume Controls
Digital Filters
Multi-bit Modulators
Switch-Cap DAC and Analog Filters
2
Single-Ended Outputs
PCM Serial Audio Output
2
High-Pass Filter
Digital Filters
Switch-Cap ADC
2
Single-Ended Inputs
Advance Product Information
http://www.cirrus.com
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
Copyright (c) Cirrus Logic, Inc. 2005 (All Rights Reserved)
MAY '05 DS686A1
CS4270
Stand-Alone Mode Feature Set
System Features
- - - - - Serial Audio Port Master or Slave Operation Single, Double, or Quad-Speed Operation Auto-mute on Static Samples 44.1 kHz 50/15 s De-emphasis Available Selectable Serial Audio Interface Formats Left-Justified up to 24-bit IS up to 24-bit High-Pass Filter Selectable Serial Audio Interface Formats Left-Justified up to 24-bit IS up to 24-bit
General Description
The CS4270 is a high-performance, integrated audio CODEC. The CS4270 performs stereo analog-to-digital (A/D) and digital-to-analog (D/A) conversion of up to 24-bit serial values at sample rates up to 216 kHz. Standard 50/15 s de-emphasis is available for sampling rates of 44.1 kHz for compatibility with digital audio programs mastered using the 50/15 s pre-emphasis technique. Integrated level translators allow easy interfacing between the CS4270 and other devices operating over a wide range of logic levels. Independently addressable high-pass filters are available for the right and left channel of the A/D. This allows the A/D to be used in a wide variety of applications where one audio channel and one DC measurement channel is desired. The CS4270's wide dynamic range, negligible distortion, and low noise make it ideal for applications such as DVD-recorders, digital televisions, set top boxes, effects processors, and automotive audio systems.
D/A Features
A/D Features
- -
Software Mode Feature Set
System Features
- - - - - - - Serial Audio Port Master or Slave Operation Internal Digital Loopback Available Selectable Auto-mute 44.1-kHz De-emphasis Filters Configurable Muting Controls Volume Control Selectable Serial Audio Interface Formats Left-Justified up to 24-bit IS up to 24-bit Right Justified 16, and 24-bit Selectable High-Pass Filter or DC Offset Calibration Selectable Serial Audio Interface Formats Left-Justified up to 24-bit IS up to 24-bit
D/A Features
A/D Features
- -
ORDERING INFORMATION
Description Package 24-Bit 192 kHz Stereo CS4270 24-TSSOP Audio CODEC 24-Bit 192 kHz Stereo CS4270 24-TSSOP Audio CODEC CDB4270 CS4270 Evaluation Board Product Pb-Free YES YES Container Order # Rail CS4270-CZZ Commercial -10 to +85 C Tape & Reel CS4270-CZZR Rail CS4270-DZZ Commercial -40 to +85 C Tape & Reel CS4270-DZZR CDB4270 Grade Temp Range
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DS686A1
CS4270
TABLE OF CONTENTS
1. PIN DESCRIPTIONS - SOFTWARE MODE ............................................................................. 6 2. PIN DESCRIPTIONS - STAND-ALONE MODE ....................................................................... 7 3. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 8 SPECIFIED OPERATING CONDITIONS ................................................................................. 8 ABSOLUTE MAXIMUM RATINGS ........................................................................................... 8 THERMAL CHARACTERISTICS.............................................................................................. 8 DAC ANALOG CHARACTERISTICS (CS4270-CZZ)............................................................... 9 DAC ANALOG CHARACTERISTICS (CS4270-DZZ)............................................................... 9 DAC COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE................ 11 ADC ANALOG CHARACTERISTICS (CS4270-CZZ)............................................................. 12 ADC ANALOG CHARACTERISTICS (CS4270-DZZ)............................................................. 13 ADC ANALOG CHARACTERISTICS - ALL MODES ............................................................. 14 ADC DIGITAL FILTER CHARACTERISTICS ........................................................................ 14 DC ELECTRICAL CHARACTERISTICS ................................................................................ 15 DIGITAL CHARACTERISTICS............................................................................................... 16 SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT................................................. 16 SWITCHING CHARACTERISTICS - IC MODE CONTROL PORT....................................... 19 SWITCHING CHARACTERISTICS - SPI CONTROL PORT.................................................. 20 4. TYPICAL CONNECTION DIAGRAM ..................................................................................... 21 5. APPLICATIONS ..................................................................................................................... 22 5.1 Stand-Alone Mode ........................................................................................................... 22 5.1.1 Recommended Power-Up Sequence ................................................................. 22 5.1.2 Master/Slave Mode ............................................................................................. 22 5.1.3 System Clocking ................................................................................................. 22 5.1.4 Clock Ratio Selection .......................................................................................... 23 5.1.5 Interpolation Filter .............................................................................................. 23 5.1.6 High-Pass Filter .................................................................................................. 23 5.1.7 Mode Selection & De-Emphasis ......................................................................... 24 5.1.8 Serial Audio Interface Format Selection ............................................................. 24 5.2 Control Port Mode ........................................................................................................... 24 5.2.1 Recommended Power-Up Sequence - Access to Control Port Mode ................ 24 5.2.2 Master / Slave Mode Selection ........................................................................... 24 5.2.3 System Clocking ................................................................................................. 25 5.2.4 Clock Ratio Selection .......................................................................................... 25 5.2.5 Internal Digital Loopback .................................................................................... 26 5.2.6 Auto-Mute ........................................................................................................... 26 5.2.7 High-Pass Filter and DC Offset Calibration ........................................................ 26 5.2.8 De-Emphasis ...................................................................................................... 27 5.2.9 Oversampling Modes .......................................................................................... 27 5.3 De-Emphasis Filter .......................................................................................................... 27 5.4 Analog Connections ........................................................................................................ 28 5.4.1 Input Connections ............................................................................................... 28 5.4.2 Output Connections ............................................................................................ 29 5.5 Mute Control .................................................................................................................... 29 5.6 Synchronization of Multiple Devices ................................................................................ 30 5.7 Grounding and Power Supply Decoupling ....................................................................... 30 6. CONTROL PORT INTERFACE .............................................................................................. 31 6.1 SPITM Mode ..................................................................................................................... 31 6.2 IC Mode .......................................................................................................................... 32 7. REGISTER QUICK REFERENCE .......................................................................................... 33 8. REGISTER DESCRIPTION .................................................................................................... 34 8.1 Chip ID - Address 01h ..................................................................................................... 34 DS686A1 3
CS4270
8.2 Power Control - Address 02h .......................................................................................... 34 8.2.1 Freeze (Bit 7) ...................................................................................................... 34 8.2.2 PDN_ADC (Bit 5) ................................................................................................ 34 8.2.3 PDN_DAC (Bit 1) ................................................................................................ 34 8.2.4 Power Down (Bit 0) ............................................................................................. 34 8.3 Mode Control - Address 03h ............................................................................................ 35 8.3.1 ADC Functional Mode & Master / Slave Mode (Bits 5:4) .................................... 35 8.3.2 Ratio Select (Bits 3:1) ......................................................................................... 35 8.3.3 PopGuard Disable (Bit 0) .................................................................................... 35 8.4 ADC and DAC Control - Address 04h ............................................................................. 35 8.4.1 ADC HPF Freeze A (Bit 7) .................................................................................. 35 8.4.2 ADC HPF Freeze B (Bit 6) .................................................................................. 36 8.4.3 Digital Loopback (Bit 5) ....................................................................................... 36 8.4.4 DAC Digital Interface Format (Bits 4:3) ............................................................... 36 8.4.5 ADC Digital Interface Format (Bit 0) ................................................................... 36 8.5 Transition Control - Address 05h ..................................................................................... 37 8.5.1 DAC Single Volume (Bit 7) .................................................................................. 37 8.5.2 Soft Ramp or Zero Cross Enable (Bits 6:5) ........................................................ 37 8.5.3 Invert Signal Polarity (Bits 4:1) ............................................................................ 37 8.5.4 De-Emphasis Control (Bit 0) ............................................................................... 38 8.6 Mute Control - Address 06h ............................................................................................. 38 8.6.1 Auto-Mute (Bit 5) ................................................................................................. 38 8.6.2 ADC Channel A & B Mute (Bits 4:3) ................................................................... 38 8.6.3 Mute Polarity (Bit 2) ............................................................................................ 38 8.6.4 DAC Channel A & B Mute (Bits 1:0) ................................................................... 38 8.7 DAC Channel A Volume Control - Address 07h .............................................................. 39 8.8 DAC Channel B Volume Control - Address 08h .............................................................. 39 10. PACKAGE DIMENSIONS .................................................................................................... 41 11. APPENDIX ....................................................................................................................... 42 12. REVISION HISTORY ............................................................................................................ 48
LIST OF FIGURES
Figure 1. Output Test Load ....................................................................................................................... 10 Figure 2. Maximum Loading ...................................................................................................................... 10 Figure 3. Master Mode Serial Audio Port Timing ...................................................................................... 17 Figure 4. Slave Mode Serial Audio Port Timing ........................................................................................ 17 Figure 5. Format 0, Left Justified up to 24-Bit Data .................................................................................. 18 Figure 6. Format 1, IS up to 24-Bit Data .................................................................................................. 18 Figure 7. Format 2, Right Justified 16-Bit Data. (Available in Control Port Mode only) Format 3, Right Justified 24-Bit Data. (Available in Control Port Mode only) ............................................ 18 Figure 8. IC Mode Control Port Timing .................................................................................................... 19 Figure 9. SPI Control Port Timing ............................................................................................................. 20 Figure 10. CS4270 Typical Connection Diagram ...................................................................................... 21 Figure 11. De-Emphasis Curve ................................................................................................................. 27 Figure 12. CS4270 Recommended Analog Input Network ....................................................................... 28 Figure 13. CS5344 Example Analog Input Network .................................................................................. 29 Figure 14. CS4270 Recommended Analog Output Filter .......................................................................... 29 Figure 15. Suggested Active-Low Mute Circuit ......................................................................................... 30 Figure 16. Control Port Timing, SPI mode ................................................................................................ 31 Figure 17. Control Port Timing, IC Mode ................................................................................................. 32 Figure 18. De-Emphasis Curve ................................................................................................................. 38 Figure 19. DAC Single-Speed (fast) Stopband Rejection ......................................................................... 42 Figure 20. DAC Single-Speed (fast) Transition Band ............................................................................... 42 4 DS686A1
CS4270
Figure 21. DAC Single-Speed (fast) Transition Band (detail) ................................................................... 42 Figure 22. DAC Single-Speed (fast) Passband Ripple ............................................................................. 42 Figure 23. DAC Single-Speed (slow) Stopband Rejection ........................................................................ 42 Figure 24. DAC Single-Speed (slow) Transition Band .............................................................................. 42 Figure 25. DAC Single-Speed (slow) Transition Band (detail) .................................................................. 43 Figure 26. DAC Single-Speed (slow) Passband Ripple ............................................................................ 43 Figure 27. DAC Double-Speed (fast) Stopband Rejection ........................................................................ 43 Figure 28. DAC Double-Speed (fast) Transition Band .............................................................................. 43 Figure 29. DAC Double-Speed (fast) Transition Band (detail) .................................................................. 43 Figure 30. DAC Double-Speed (fast) Passband Ripple ............................................................................ 43 Figure 31. DAC Double-Speed (slow) Stopband Rejection ...................................................................... 44 Figure 32. DAC Double-Speed (slow) Transition Band ............................................................................. 44 Figure 33. DAC Double-Speed (slow) Transition Band (detail) ................................................................. 44 Figure 34. DAC Double-Speed (slow) Passband Ripple ........................................................................... 44 Figure 35. DAC Quad-Speed (fast) Stopband Rejection .......................................................................... 44 Figure 36. DAC Quad-Speed (fast) Transition Band ................................................................................. 44 Figure 37. DAC Quad-Speed (fast) Transition Band (detail) ..................................................................... 45 Figure 38. DAC Quad-Speed (fast) Passband Ripple ............................................................................... 45 Figure 39. DAC Quad-Speed (slow) Stopband Rejection ......................................................................... 45 Figure 40. DAC Quad-Speed (slow) Transition Band ............................................................................... 45 Figure 41. DAC Quad-Speed (slow) Transition Band (detail) ................................................................... 45 Figure 42. DAC Quad-Speed (slow) Passband Ripple ............................................................................. 45 Figure 43. ADC Single-Speed Mode Stopband Rejection ........................................................................ 46 Figure 44. ADC Single-Speed Mode Transition Band ............................................................................... 46 Figure 45. ADC Single-Speed Mode Transition Band (Detail) .................................................................. 46 Figure 46. ADC Single-Speed Mode Passband Ripple ............................................................................. 46 Figure 47. ADC Double-Speed Mode Stopband Rejection ....................................................................... 46 Figure 48. ADC Double-Speed Mode Transition Band ............................................................................. 46 Figure 49. ADC Double-Speed Mode Transition Band (Detail) ................................................................. 47 Figure 50. ADC Double-Speed Mode Passband Ripple ........................................................................... 47 Figure 51. ADC Quad-Speed Mode Stopband Rejection .......................................................................... 47 Figure 52. ADC Quad-Speed Mode Transition Band ................................................................................ 47 Figure 53. ADC Quad-Speed Mode Transition Band (Detail) ................................................................... 47 Figure 54. ADC Quad-Speed Mode Passband Ripple .............................................................................. 47
LIST OF TABLES
Table 1. Speed Modes .............................................................................................................................. Table 2. Clock Ratios - Stand-Alone Mode ............................................................................................... Table 3. CS4270 Stand-Alone Mode Control............................................................................................ Table 4. Speed Modes .............................................................................................................................. Table 5. Clock Ratios - Control Port Mode................................................................................................ Table 6. Analog Input Design Parameters ................................................................................................ Table 7. Memory Address Pointer............................................................................................................. Table 8. Functional Mode Selection.......................................................................................................... Table 9. MCLK Divider Configuration........................................................................................................ Table 10. DAC Digital Interface Formats .................................................................................................. Table 11. ADC Digital Interface Formats .................................................................................................. Table 12. Soft Cross or Zero Cross Mode Selection................................................................................. Table 13. Digital Volume Control .............................................................................................................. 22 23 24 25 25 28 32 35 35 36 36 37 39
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CS4270 1. PIN DESCRIPTIONS - SOFTWARE MODE
SDIN LRCK MCLK SCLK VD DGND SDOUT VLC SDA/CDOUT SCL/CCLK AD0/CS AD1/CDIN
1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13
MUTEB AOUTB AOUTA MUTEA AGND VA FILT+ VQ AINB AINA RST AD2
Pin Name
SDIN LRCK MCLK SCLK VD DGND SDOUT VLC SDA/CDOUT SCL/CCLK AD0/CS AD1/CDIN AD2 RST AINA AINB VQ FILT+ VA AGND MUTEA MUTEB AOUTA AOUTB
#
1
Pin Description
Serial Audio Data Input (Input) - Input for two's complement serial audio data. Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the serial audio data line. Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters. Serial Clock (Input/Output) - Serial clock for the serial audio interface. Digital Power (Input) - Positive power supply for the digital section. Digital Ground (Input) - Ground reference for the internal digital section. Serial Audio Data Output (Output) - Output for two's complement serial audio data. Control Port Power (Input) - Determines the signal level for the control port. Serial Control Data (Input/Output) - SDA is a data I/O in IC mode. CDOUT is the output data line for the control port interface in SPI mode. Serial Control Port Clock (Input) - Serial clock for the serial control port. Address Bit 0 (IC) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in IC mode. CS is the chip select signal for SPI format. Address Bit 1 (IC) / Serial Control Data (Input) - AD1 is a chip address pin in IC mode. CDIN is the input data line for the control port interface in SPI mode. Address Bit 2 (IC) (Input) - AD2 is a chip address pin in IC mode. Reset (Input) - The device enters a low power mode when low. Analog Input (Input) - The full-scale analog input level is specified in the ADC Analog Characteristics specification table. Quiescent Voltage (Output) - Filter connection for internal quiescent voltage. Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits. Analog Power (Input) - Positive power for the analog sections. Analog Ground (Input) - Ground reference. Must be connected to analog ground. Mute Control (Output) - Each pin is active during power-up initialization, reset, muting, when master clock to left/right clock frequency ratio is incorrect, or power-down. Analog Audio Output (Output) - The full-scale output level is specified in the DAC Analog Characteristics specification table.
2
3
4 5 6 7 8 9 10 11 12 13 14 15 16
17 18 19
20 21 24 22 23
6
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CS4270 2. PIN DESCRIPTIONS - STAND-ALONE MODE
SDIN LRCK MCLK SCLK VD DGND SDOUT VLC M1 M0 IS/LJ MDIV1
1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13
MUTEB AOUTB AOUTA MUTEA AGND VA FILT+ VQ AINB AINA RST MDIV2
Pin Name
SDIN LRCK MCLK SCLK VD DGND SDOUT (M/S) VLC M1 M0
#
1
Pin Description
Serial Audio Data Input (Input) - Input for two's complement serial audio data. Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the serial audio data line. Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters. Serial Clock (Input/Output) - Serial clock for the serial audio interface. Digital Power (Input) - Positive power supply for the digital section. Digital Ground (Input) - Ground reference for the internal digital section. Serial Audio Data Output (Output) - Output for two's complement serial audio data. This pin must be pulled-up or pulled-down to select Master or Slave Mode. Control Port Power (Input) - Determines the signal level for the control port. Mode Selection (Input) - Determines the operational mode of the device. Serial Audio Interface Select (Input) - Selects either the left-justified orIS format for the Serial Audio Interface. MCLK Divide (Input) - Configures MCLK divider to divide by 1, 1.5, 2, or 4. Reset (Input) - The device enters a low power mode when low. Analog Input (Input) - The full-scale analog input level is specified in the ADC Analog Characteristics specification table. Quiescent Voltage (Output) - Filter connection for internal quiescent voltage. Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits. Analog Power (Input) - Positive power for the analog sections. Analog Ground (Input) - Ground reference. Must be connected to analog ground. Mute Control (Output) - Each pin is active during power-up initialization, reset, muting, when master clock to left/right clock frequency ratio is incorrect, or power-down. Analog Audio Output (Output) - The full-scale output level is specified in the DAC Analog Characteristics specification table.
2
3
4 5 6 7 8 9 10 11 12 13 14 15 16
17 18
IS/LJ
MDIV1 MDIV2 RST AINA AINB VQ FILT+
VA
AGND MUTEA MUTEB AOUTA AOUTB
19 20 21 24 22 23
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CS4270 3. CHARACTERISTICS AND SPECIFICATIONS
(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and TA = 25C.)
SPECIFIED OPERATING CONDITIONS
(AGND = 0 V; all voltages with respect to ground.) Parameters Analog Digital Control Port Interface Ambient Operating Temperature (Power Applied) (-CZZ) (-DZZ)
DC Power Supplies:
Symbol VA VD VLC TA-CZZ TA-DZZ
Min 3.1 3.1 1.7 -10 -40
Nom 5.0 3.3 3.3 -
Max 5.25 5.25 5.25 +70 +85
Units V V V C C
ABSOLUTE MAXIMUM RATINGS
(AGND = DGND = 0 V, All voltages with respect to ground.) (Note 1) Parameter
DC Power Supplies:
Symbol Analog Digital Control Port Interface (Note 2) Control Port Interface Digital Interface VA VD VLC Iin VIN VIND-C VIND-D TAC Tstg
Min -0.3 -0.3 -0.3 -10 AGND-0.7 -0.3 -0.3 -50 -65
Typ -
Max +6.0 +6.0 +6.0 +10 VA+0.7 VLC+0.3 VD+0.3 +95 +150
Units V V V mA V V V C C
Input Current Analog Input Voltage Digital Input Voltage
Ambient Operating Temperature (Power Applied) Storage Temperature
Notes: 1. Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 2. Any pin except supplies. Transient currents of up to 100 mA on the analog input pins will not cause SRC latch-up.
THERMAL CHARACTERISTICS
Parameters
Allowable Junction Temperature Junction to Ambient Thermal Impedance (Note 3)
Symbol
Min -
Typ 70 60 105 80
Max 135 -
Units C C/W C/W C/W C/W
(Multi-layer PCB) TSSOP (Multi-layer PCB) SOIC (Single-layer PCB) TSSOP (Single-layer PCB) SOIC
JA-TM JA-SM JA-TS JA-SS
3. JA is specified according to JEDEC specifications for multi-layer PCBs.
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CS4270 DAC ANALOG CHARACTERISTICS (CS4270-CZZ)
(Full-Scale Output Sine Wave, 997 Hz (Note 4), Fs = 48/96/192 kHz; Test load RL = 3 k, CL = 10 pF (see Figure 1). Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified.) VA = 5V Parameter
Dynamic Range 18 to 24-Bit A-weighted 16-Bit Total Harmonic Distortion + Noise 18 to 24-Bit
VA = 3.3V Max -89 -76 -36 -87 -67 -27 Min 97 94 90 87 Typ 103 100 96 93 -95 -80 -40 -93 -73 -33 Max -89 -74 -34 -87 -67 -27 Unit dB dB dB dB dB dB dB dB dB dB
Min unweighted A-weighted unweighted 0 dB -20 dB -60 dB 0 dB -20 dB -60 dB 99 96 90 87 -
Typ 105 102 96 93 -95 -82 -42 -93 -73 -33
16-Bit
DAC ANALOG CHARACTERISTICS (CS4270-DZZ)
(Full-Scale Output Sine Wave, 997 Hz (Note 4), Fs = 48/96/192 kHz; Test load RL = 3 k, CL = 10 pF (see Figure 1). Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified.) VA = 5V Parameter
Dynamic Range 18 to 24-Bit A-weighted 16-Bit Total Harmonic Distortion + Noise 18 to 24-Bit
VA = 3.3V Max -85 -72 -32 -83 -63 -23 Min 93 90 86 83 Typ 103 100 96 93 -95 -80 -40 -93 -73 -33 Max -85 -70 -30 -83 -63 -23 Unit dB dB dB dB dB dB dB dB dB dB
Min unweighted A-weighted unweighted 0 dB -20 dB -60 dB 0 dB -20 dB -60 dB 95 92 86 83 -
Typ 105 102 96 93 -95 -82 -42 -93 -73 -33
16-Bit
4. One-half LSB of triangular PDF dither added to data.
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CS4270 DAC ANALOG CHARACTERISTICS - ALL MODES
Parameter
Interchannel Isolation
Symbol (1 kHz)
Min -100 0.640*VA
Typ 100 0.1
Max 0.25 +100
Unit dB dB ppm/C Vpp A k pF
DC Accuracy
Interchannel Gain Mismatch Gain Drift
Analog Output
Full Scale Output Voltage Max DC Current draw from AOUTA or AOUTB Max AC-Load Resistance (see Figure 2) Max Load Capacitance (see Figure 2) Output Impedance of AOUTA and AOUTB
0.688*VA 10 3 100 100
0.739*VA -
IOUTmax RL CL ZOUT
-
3.3 F
Capacitive Load -- C (pF) L
125 100 75 50 25 Safe Operating Region
AOUTx R C
V out
L
L
AGND
2.5 3
5
10
15
20
Resistive Load -- RL (k )
Figure 1. Output Test Load
Figure 2. Maximum Loading
10
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CS4270 DAC COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE
(The filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired sample rate by multiplying the given characteristic by Fs.) (See Note 5) Parameter
Single-Speed Mode Passband (Note 6) Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation Group Delay De-emphasis Error (Note 8)
Symbol to -0.05 dB corner to -3 dB corner
Min 0 0 -.01 .5465
Typ 10/Fs 5/Fs 2.5/Fs
Max .4780 .4996 +.08 +1.5/+0 +.05/-.25 -.2/-.4 .4650 .4982 +.2 0.397 0.476 +0.00004 -
Unit Fs Fs dB Fs dB s dB dB dB Fs Fs dB Fs dB s Fs Fs dB Fs dB s
(Note 7) tgd Fs = 32 kHz Fs = 44.1 kHz Fs = 48 kHz to -0.1 dB corner to -3 dB corner
50 0 0 -.05 .5770
Double-Speed Mode
Passband (Note 6) Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation Group Delay
(Note 7) tgd to -0.1 dB corner to -3 dB corner
55 0 0 0 0.7
Quad-Speed Mode
Passband (Note 6) Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation Group Delay
(Note 7) tgd
51 -
5. Amplitude vs. Frequency plots of this data are available in Section 11. "Appendix" on page 42. See Figures 19 through 42. 6. Response is clock dependent and will scale with Fs. 7. For Single-Speed Mode, the Measurement Bandwidth is 0.5465 Fs to 3 Fs. For Double-Speed Mode, the Measurement Bandwidth is 0.577 Fs to 1.4 Fs. For Quad-Speed Mode, the Measurement Bandwidth is 0.7 Fs to 1 Fs. 8. De-emphasis is available only in Single-Speed Mode.
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CS4270 ADC ANALOG CHARACTERISTICS (CS4270-CZZ)
Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified. Input is 1 kHz sine wave.
VA = 5V Parameter Single-Speed Mode Dynamic Range Total Harmonic Distortion + Noise Fs = 48 kHz Symbol Min Typ Max Min VA = 3.3V Typ Max Unit
A-weighted unweighted (Note 9) -1 dB -20 dB -60 dB
THD+N
99 96 -
105 102 -98 -82 -42
-92 -
96 93 -
102 99 -95 -79 -39
-89 -
dB dB dB dB dB
Double-Speed Mode Dynamic Range
Fs = 96 kHz 99 96 THD+N -98 -82 -42 -95 -92 -95 -79 -39 -87 -89 dB dB dB dB 105 102 99 96 93 102 99 96 dB dB dB
A-weighted unweighted 40 kHz bandwidth unweighted (Note 9) -1 dB -20 dB -60 dB -1 dB
Total Harmonic Distortion + Noise
40 kHz bandwidth
Quad-Speed Mode Dynamic Range
Fs = 192 kHz 99 96 THD+N -98 -82 -42 -95 -92 -95 -79 -39 -87 -89 dB dB dB dB 105 102 99 96 93 102 99 96 dB dB dB
A-weighted unweighted 40 kHz bandwidth unweighted (Note 9) -1 dB -20 dB -60 dB -1 dB
Total Harmonic Distortion + Noise
40 kHz bandwidth
9. Referred to the typical full-scale input voltage.
12
DS686A1
CS4270 ADC ANALOG CHARACTERISTICS (CS4270-DZZ)
Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified. Input is 1 kHz sine wave.
VA = 5V Parameter Single-Speed Mode Dynamic Range Total Harmonic Distortion + Noise Fs = 48 kHz Symbol Min Typ Max Min VA = 3.3V Typ Max Unit
A-weighted unweighted (Note 10) -1 dB -20 dB -60 dB
THD+N
97 94 -
105 102 -98 -82 -42
-90 -
94 91 -
102 99 -95 -79 -39
-87 -
dB dB dB dB dB
Double-Speed Mode Dynamic Range
Fs = 96 kHz
A-weighted unweighted 40 kHz bandwidth unweighted (Note 10) -1 dB -20 dB -60 dB -1 dB
THD+N
97 94 -
105 102 99
-
94 91 -
102 99 96
-
dB dB dB
Total Harmonic Distortion + Noise
40 kHz bandwidth
Quad-Speed Mode Dynamic Range
-
-98 -82 -42 -95
-90 -
-
-95 -79 -39 -87
-87 -
dB dB dB dB
Fs = 192 kHz
A-weighted unweighted 40 kHz bandwidth unweighted (Note 10) -1 dB -20 dB -60 dB -1 dB
THD+N
97 94 -
105 102 99
-
94 91 -
102 99 96
-
dB dB dB
Total Harmonic Distortion + Noise
40 kHz bandwidth
-
-98 -82 -42 -95
-90 -
-
-95 -79 -39 -87
-87 -
dB dB dB dB
10. Referred to the typical full-scale input voltage.
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CS4270 ADC ANALOG CHARACTERISTICS - ALL MODES
Interchannel Isolation
-
90
-
dB
DC Accuracy
Interchannel Gain Mismatch Gain Error Gain Drift
-3 -100
0.1 -
3 +100
dB % ppm/C
Analog Input Characteristics
Full-scale Input Voltage Input Impedance
0.54*V A -
0.56*VA 300
0.58*V A -
Vpp k
ADC DIGITAL FILTER CHARACTERISTICS (Note 11)
(Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified) Parameter Single-Speed Mode
Passband Passband Ripple Stopband Stopband Attenuation Group Delay Interchannel Phase Deviation (-0.1 dB)
Symbol (Note 12) (Note 12) tgd
Min 0 -0.1 0.58 -95 -
Typ 12/Fs 9/Fs 5/Fs 1 20 10
Max 0.47 0.035 0.0001 0.45 0.035 0.0001 0.24 0.035 0.0001 -
Unit Fs dB Fs dB s deg Fs dB Fs dB s deg Fs dB Fs dB s deg Hz Hz deg
Double-Speed Mode
Passband Passband Ripple Stopband Stopband Attenuation Group Delay Interchannel Phase Deviation (-0.1 dB)
(Note 12) (Note 12) tgd
0 -0.1 0.68 -92 -
Quad-Speed Mode
Passband Passband Ripple Stopband Stopband Attenuation Group Delay Interchannel Phase Deviation (-0.1 dB)
(Note 12) (Note 12) tgd
0 -0.1 0.78 -97 -
High-Pass Filter Characteristics
Frequency Response Phase Deviation -3.0 dB -0.13 dB @ 20 Hz
(Note 13) (Note 13) -
14
DS686A1
CS4270
Parameter
Passband Ripple Filter Settling Time
Symbol
Min -
Typ 10 /Fs
5
Max 0
Unit dB s
11. Plots of this data are contained in Section 11. "Appendix" on page 42. See Figures 43 through 54. 12. The filter frequency response scales precisely with Fs. 13. Response shown is for Fs equal to 48 kHz. Filter characteristics scale with Fs.
DC ELECTRICAL CHARACTERISTICS
(TA = 25 C; AGND=DGND=0, all voltages with respect to ground; MLCK=12.288 MHz; Master Mode) Parameter Power Supply
Power Supply Current (Normal Operation)
Symbol VA = 5 V VA = 3.3 V VD, VLC = 5 V VD, VLC = 3.3 V VA = 5 V VD, VLC = 5 V IA IA ID ID IA ID PSRR VQ
Min -
Typ 31 27 29 20 1.51 0.45 221 255 9.8 60 VA/2 1 25 VA 10 18 0 VA 3
Max 40 35 38 29 296 323 -
Unit mA mA mA mA mA mA mW mW mW dB VDC A k VDC A k V V mA
Power Supply Current (Power-Down Mode) (Note 14) Power Consumption VA = 5 V, VD = VLC= 3.3 V
Normal Operation VA = 5 V, VD = VLC = 5 V Normal Operation Power-Down Mode (Note 14) (Note 15)
Power Supply Rejection Ratio (1 kHz)
Common Mode Voltage
Nominal Common Mode Voltage Maximum DC Current Source/Sink from VQ VQ Output Impedance
Positive Voltage Reference
FILT+ Nominal Voltage Maximum DC Current Source/Sink from FILT+ FILT+ Output Impedance
FILT+
-
Mute Control
MUTEA, MUTEB Low-Level Output Voltage MUTEA, MUTEB High-Level Output Voltage Maximum MUTEA & MUTEB Drive Current
14. Power Down Mode is defined as RST = Low with all clocks and data lines held static. 15. Valid with the recommended capacitor values on FILT+ and VQ as shown in the Typical Connection Diagram.
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15
CS4270 DIGITAL CHARACTERISTICS
Parameter (Note 16)
High-Level Input Voltage Low-Level Input Voltage
Symbol Serial Port Control Port Serial Port Control Port Serial Port Control Port MUTEA, MUTEB VIH VIL VOH
Min 0.7xVD 0.7xVLC VD - 1.0 VLC - 1.0 VA - 1.0 -10
Typ -
Max 0.2xVD 0.2xVLC 0.4 10
Units V V V V V V V V A
High-Level Output Voltage at Io = 2 mA
Low-Level Output Voltage at Io = 2 mA Input Leakage Current
VOL Iin
16. Serial Port signals include: SCLK, LRCK, SDOUT, SDIN Control Port signals include: SDA/CDOUT, SCL/CCLK, AD1/CDIN, AD0/CS, RST
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT
(Logic "0" = AGND = 0 V; Logic "1" = VD, CL = 20 pF) Parameter
Sample Rate
Symbol Single-Speed Mode Double-Speed Mode Quad-Speed Mode Stand-Alone Mode Control Port Mode Fs Fs Fs fmclk fmclk
Min 4 50 100 1.024 1.024 40 -
Typ 50 50
1 ----------------( 64 )Fs
Max 54 108 216 55.296 55.296 60 10 32 60 -
Unit kHz kHz kHz MHz MHz ns % s % ns ns ns ns % s s
MCLK Specifications
MCLK Frequency (Note 17) MCLK Duty Cycle
Master Mode
LRCK Duty Cycle SCLK Period SCLK Duty Cycle SCLK falling to LRCK edge SCLK falling to SDOUT valid SDIN valid to SCLK rising setup time SCLK rising to SDIN hold time
50 50 -
tslr tsdo tsdis tsdih
-10 16 20 40
Slave Mode
LRCK Duty Cycle SCLK Period (Note 17)
Single-Speed Mode Double-Speed Mode Quad-Speed Mode
tsclkw tsclkw tsclkw
1 -------------------( 128 )Fs 1 -------------------( 128 )Fs 1 ----------------( 64 )Fs
50 -
55 10
s ns ns DS686A1
SCLK Duty Cycle SCLK falling to LRCK edge
tslr
45 -10
16
CS4270
SCLK falling to SDOUT valid SDIN valid to SCLK rising setup time SCLK rising to SDIN hold time
tsdo tsdis tsdih
16 20
-
32 -
ns ns ns
17. In Control Port Mode, MCLK Frequency and Functional Mode Select bits must be configured according to Table 5, Table 9, and Table 8
LRCK O utput
t SCLK O utput t SDO UT
slr
sdo
t SDIN
sdis
t
sdih
Figure 3. Master Mode Serial Audio Port Timing
LRCK Input
t SCLK Input t SDO UT
slr
t sdo
sclkw
t SDIN
sdis
t
sdih
Figure 4. Slave Mode Serial Audio Port Timing
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17
CS4270
LRCK SCLK
Left Channel
Right Channel
SDATA
MSB -1 -2 -3 -4 -5
+5 +4 +3 +2 +1 LSB
MSB -1 -2 -3 -4
+5 +4 +3 +2 +1 LSB
Figure 5. Format 0, Left Justified up to 24-Bit Data
LRCK SCLK
Left Channel
Right Channel
SDATA
MSB -1 -2 -3 -4 -5
+5 +4 +3 +2 +1 LSB
MSB -1 -2 -3 -4
+5 +4 +3 +2 +1 LSB
Figure 6. Format 1, IS up to 24-Bit Data
LRCK
Left Channel
R ight Channel
SCLK
SDATA
LS B
MS B-1 -2 -3 -4 -5 -6
B +6 +5 +4 +3 +2 +1 LS
MS -1 -2 -3 -4 -5 -6 B
B +6 +5 +4 +3 +2 +1 LS
32 clo cks
Figure 7. Format 2, Right Justified 16-Bit Data. (Available in Control Port Mode only) Format 3, Right Justified 24-Bit Data. (Available in Control Port Mode only)
18
DS686A1
CS4270 SWITCHING CHARACTERISTICS - IC MODE CONTROL PORT
(Inputs: logic 0 = DGND, logic 1 = VLC) Parameter IC Mode
SCL Clock Frequency RST Rising Edge to Start Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling SDA Setup time to SCL Rising Rise Time of Both SDA and SCL Lines Fall Time of Both SDA and SCL Lines Setup Time for Stop Condition
Symbol fscl tirs tbuf thdst tlow thigh tsust (Note 18) thdd tsud tr tf tsusp
Min 500 4.7 4.0 4.7 4.0 4.7 0 250 4.7
Max 100 1 300 -
Unit kHz ns s s s s s s ns s ns s
18. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
RST t irs Stop SDA t buf
SCL Repeated Start
Start
Stop
t hdst
t high
t
hdst
tf
t susp
t
low
t
hdd
t sud
t sust
tr
Figure 8. IC Mode Control Port Timing
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CS4270 SWITCHING CHARACTERISTICS - SPI CONTROL PORT
(Inputs: logic 0 = DGND, logic 1 = VLC) Parameter SPI Mode
CCLK Clock Frequency RST Rising Edge to CS Falling CCLK Edge to CS Falling CS High Time Between Transmissions CS Falling to CCLK Edge CCLK Low Time CCLK High Time CDIN to CCLK Rising Setup Time CCLK Rising to DATA Hold Time Rise Time of CCLK and CDIN Fall Time of CCLK and CDIN
Symbol fsclk tsrs (Note 19) tspi tcsh tcss tscl tsch tdsu (Note 20) (Note 21) (Note 21) tdh tr2 tf2
Min 500 500 1.0 20 82 82 40 15 -
Max 6 100 100
Unit MHz ns ns s ns ns ns ns ns ns ns
19. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times. 20. Data must be held for sufficient time to bridge the transition time of CCLK. 21. For FSCK < 1 MHz
RST
t srs
CS t spi t css CCLK t r2
CDIN
t scl
t sch
t csh
t f2
t dsu t dh
Figure 9. SPI Control Port Timing
20
DS686A1
CS4270 4. TYPICAL CONNECTION DIAGRAM
+3.3 V to 5 V
0.1 F 1 F
5.1
1.
0.1 F
1 F
+3.3 V to 5 V VA FILT+
47 F 0.1 F
1.
VD
2.
GND or VD
AGND
1 F 0.1 F
47 k
VQ Analog Input Network
(see Figures 12 & 13)
SDOUT (M/S) SDIN
Audio Data Processor
AINA AINB MCLK Timing Logic & Clock
CS4270
AD2 (MDIV1) Power Down and Mode Settings (Control Port) AD1 (MDIV2) AD0 / CS (I2S/LJ) SDA / CDIN (M1) SCL / CCLK (M0) RST
SCLK LRCK
MUTEA AOUTA AOUTB MUTEB
Analog Conditioning & Mute
(see Figures 14 & 15)
2 k +1.8 V to 5 V
3.
2 k
3.
VLC DGND
1.
If using separate supplies for VA and VD, 5.1 resistor not needed. See "Grounding and Power Supply Decoupling."
2.
Use a 47 k pull-down to select Master Mode or 47 k pull-up to VD to select Slave Mode. See "Master/Slave Mode Selection."
3.
Use pull-up resistors in Software Mode. In Hardware Mode, use pull-up or pull-down. See "Mode Selection & De-Emphasis."
Figure 10. CS4270 Typical Connection Diagram
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21
CS4270 5. APPLICATIONS
5.1 Stand-Alone Mode
5.1.1 Recommended Power-Up Sequence
Reliable power-up can be accomplished by keeping the device in reset until the power supplies, clocks and configuration pins are stable. It is also recommended that reset be enabled if the analog or digital supplies drop below the minimum specified operating voltages to prevent power glitch related issues.
5.1.2 Master/Slave Mode
The CS4270 supports operation in either Master Mode or Slave Mode. In Master Mode, LRCK and SCLK are outputs and are synchronously generated on-chip. LRCK is equal to Fs and SCLK is equal to 64x Fs. In Slave Mode, LRCK and SCLK are inputs, requiring external generation that is synchronous to MCLK. It is recommended that SCLK be 48x or 64x Fs to maximize system performance. In Stand-Alone Mode, the CS4270 will enter Slave Mode when SDOUT (M/S) is pulled low through a 47 k resistor. Master Mode may be accessed by placing a 47 k pull-up to VD on the SDOUT (M/S) pin. Configuration of clock ratios in each of these modes is outlined in Table 2.
5.1.3 System Clocking
The CS4270 will operate at sampling frequencies from 4 kHz to 216 kHz. This range is divided into three speed modes as shown in Table 1 . Mode Single-Speed Double-Speed Quad-Speed Sampling Frequency 4-54 kHz 50-108 kHz 100-216 kHz
Table 1. Speed Modes
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CS4270
5.1.4 Clock Ratio Selection
Depending on whether the CS4270 is in Master or Slave Mode, different MCKL/LRCK and SCLK/LRCK ratios may be used. These ratios are shown in the Table 2. Master Mode MCLK/LRCK 256 Single-Speed 384 512 1024 128 Double-Speed 192 256 512 64 Quad-Speed 96 128 256 Slave Mode MCLK/LRCK 256 Single-Speed 384 512 1024 128 Double-Speed 192 256 512 64 Quad-Speed 96 128 256 SCLK/LRCK 32, 48, 64, 128 32, 48, 64, 96 32, 48, 64, 128 32, 48, 64, 96 32, 48, 64 32, 48, 64 32, 48, 64 32, 48, 64 32, 48, 64 32, 48, 64 32, 48, 64 32, 48, 64 LRCK Fs Fs Fs Fs Fs Fs Fs Fs Fs Fs Fs Fs MDIV2 0 0 1 1 0 0 1 1 0 0 1 1 MDIV1 0 1 0 1 0 1 0 1 0 1 0 1 SCLK/LRCK 64 64 64 64 64 64 64 64 64 64 64 64 LRCK Fs Fs Fs Fs Fs Fs Fs Fs Fs Fs Fs Fs MDIV2 0 0 1 1 0 0 1 1 0 0 1 1 MDIV1 0 1 0 1 0 1 0 1 0 1 0 1
Table 2. Clock Ratios - Stand-Alone Mode
5.1.5
Interpolation Filter
In Stand-Alone Mode, the fast roll-off interpolation filter is used. Filter specifications can be found in Section 3. Plots of the data are contained in Section 11. "Appendix" on page 42.
5.1.6 High-Pass Filter
The operational amplifiers in the input circuitry driving the CS4270 may generate a small DC offset into the ADC. The CS4270 includes a high-pass filter after the decimator to remove any DC offset which could result in recording a DC level, possibly yielding "clicks" when switching between devices in a multichannel system. In Stand-Alone Mode, the high-pass filter continuously subtracts a measure of the DC offset from the output of the decimation filter This function cannot be disabled in Stand-Alone Mode. DS686A1 23
CS4270
5.1.7 Mode Selection & De-Emphasis
The sample rate, Fs, can be adjusted from 4 kHz to 216 kHz and De-emphasis, optimized for 44.1 kHz, is available in Single-Speed Mode. In Stand-Alone Master Mode, the CS4270 must be set to the proper mode via the mode pins, M1 and M0. In Slave Mode, the CS4270 auto-detects Speed Mode and the M0 pin becomes De-emphasis select. Stand-alone definitions of the mode pins are shown in Table 3. Mode 1 0 0 1 1 Mode 0 0 1 0 1 Mode Single-Speed Mode Single-Speed Mode Double-Speed Mode Quad-Speed Mode Sample Rate (Fs) 4 kHz - 54 kHz 4 kHz - 54 kHz 50 kHz - 108 kHz 100 kHz - 216 kHz De-Emphasis Off 44.1 kHz Off Off
Table 3. CS4270 Stand-Alone Mode Control
5.1.8 Serial Audio Interface Format Selection
Either IS or Left-Justified serial audio data format may be selected in Stand-Alone Mode. The selection will affect both the input and output format. Placing a 10 k pull-up to VD on the IS/LJ pin will select the IS format, while placing a 10 k pull-down to DGND on the IS/LJ pin will select the left justified format.
5.2
Control Port Mode
5.2.1 Recommended Power-Up Sequence - Access to Control Port Mode
1. Pull RST low until the power supply, MCLK, and LRCK are stable. 2. Release RST. The control port will be accessible. 3. Initiate a SPI or IC transaction as described in Section 6.1 or Section 6.2, respectively.
5.2.2 Master / Slave Mode Selection
The CS4270 supports operation in either Master Mode or Slave Mode. In Master Mode, LRCK and SCLK are outputs and are synchronously generated on-chip. LRCK is equal to Fs and SCLK is equal to 64x Fs. In Slave Mode, LRCK and SCLK are inputs, requiring external generation that is synchronous to MCLK. It is recommended that SCLK be 48x or 64x Fs to maximize system performance. Configuration of clock ratios in each of these modes will be outlined in the Table 10 and Table 9. In Control Port Mode the CS4270 will default to Slave Mode. The user may change this default setting by changing the status of the M/S bits in the Functional Control Register (03h).
24
DS686A1
CS4270
5.2.3 System Clocking
The CS4270 will operate at sampling frequencies from 4 kHz to 216 kHz. This range is divided into three speed modes as shown in Table 4. Mode Single-Speed Double-Speed Quad-Speed Sampling Frequency 4-54 kHz 50-108 kHz 100-216 kHz
Table 4. Speed Modes
5.2.4 Clock Ratio Selection
In Control Port Master Mode, the user must configure the mode bits (M0, M1, M2) to set the speed mode and select the appropriate clock ratios. Depending on whether the CS4270 is in Master or Slave Mode, different MCLK/LRCK and SCLK/LRCK ratios may be used. These ratios as well as the Control Port Register Bits are shown in Table 5, Table 9 and Section 8.3 on page 35. Master Mode MCLK/LRCK 256 384 Single-Speed 512 768 1024 128 192 Double-Speed 256 384 512 64 96 Quad-Speed 128 192 256 MCLK/LRCK 256 384 Single-Speed 512 768 1024 SCLK/LRCK 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 Slave Mode SCLK/LRCK 32, 64, 128 32, 48, 64, 96, 128 32, 64, 128 32, 48, 64, 96, 128 32, 64, 128 LRCK Fs Fs Fs Fs Fs MCLK Freq<2> 0 0 0 0 1 MCLK Freq<1> 0 0 1 1 0 MCLK Freq<0> 0 1 0 1 0 LRCK Fs Fs Fs Fs Fs Fs Fs Fs Fs Fs Fs Fs Fs Fs Fs MCLK Freq<2> 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 MCLK Freq<1> 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 MCLK Freq<0> 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0
Table 5. Clock Ratios - Control Port Mode
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25
CS4270
Master Mode 128 192 Double-Speed 256 384 512 64 96 Quad-Speed 128 192 256 32, 48, 64 32, 48, 64 32, 48, 64 32, 48, 64 32, 64 32 48, 64 32, 64 48, 64 32, 64 Fs Fs Fs Fs Fs Fs Fs Fs Fs Fs 0 0 0 0 1 0 0 0 0 1 0 0 1 1 0 0 0 1 1 0 0 1 0 1 0 0 1 0 1 0
Table 5. Clock Ratios - Control Port Mode (Continued)
5.2.5 Internal Digital Loopback
In Control Port Mode, the CS4270 supports an internal digital loopback mode in which the output of the ADC is routed to the input of the DAC. This mode may be activated by setting the Digital Loopback bit in the ADC & DAC Ctrl register (04h). When this bit is set, the status of the DAC_DIF(4:3) bits in register 04h will be disregarded by the CS4270. Any changes made to the DAC_DIF(4:3) bits while the Digital Loopback bit is set will have no impact on operation until the Digital Loopback bit is released, at which time the Digital Interface Format of the DAC will operate according to the format selected in the DAC_DIF(4:3) bits. While the Digital Loopback bit is set, data will be present on the SDOUT pin in the format selected in the ADC_DIF(0) bit in register 04h.
5.2.6 Auto-Mute
The Auto-Mute function is controlled by the status of the Auto Mute bit in the Mute register. When set, the DAC output will mute following the reception of 8192 consecutive audio samples of static 0 or -1. A single sample of non-static data will release the mute. Detection and muting are done independently for each channel. The common mode on the output will be retained and the Mute Control pin for that channel will become active during the mute period. The muting function is affected, similar to volume control changes, by the Soft and ZeroCross bits in the Transition and Control register. The Auto Mute bit is set by default.
5.2.7 High-Pass Filter and DC Offset Calibration
The input circuitry driving the CS4270 may generate a small DC offset into the A/D converter. The CS4270 includes a high-pass filter after the decimator to remove any DC offset which could result in recording a DC level, possibly yielding "clicks" when switching between devices in a multichannel system. The high-pass filter continuously subtracts a measure of the DC offset from the output of the decimation filter. The high-pass filter can be enabled if the hpf_freeze bit is set during normal operation, the current value of the DC offset for the corresponding channel is frozen and this DC offset will continue to be subtracted from the conversion result. This feature makes it possible to perform a system DC offset calibration by: 1. Running the CS4270 with the high-pass filter enabled until the filter settles. See the Digital Filter Characteristics for filter settling time. 2. Disabling the high-pass filter and freezing the stored DC offset. A system calibration performed in this way will eliminate offsets anywhere in the signal path between the calibration point and the CS4270. 26 DS686A1
CS4270
5.2.8 De-Emphasis
One de-emphasis mode is available via the Control Port and is optimized for 44.1 kHz sampling rate.
5.2.9 Oversampling Modes
The CS4270 operates in one of three oversampling modes based on the input sample rate. Mode selection is determined by the FM_&_M/S_Mode[1:0] bits in the Functional Mode register (03h). Single-Speed mode supports input sample rates up to 54 kHz and uses a 128x oversampling ratio. Double-Speed mode supports input sample rates up to 108 kHz and uses an oversampling ratio of 64x. Quad-Speed mode supports input sample rates up to 216 kHz and uses an oversampling ratio of 32x. See Table 10 for Control Port Mode settings.
5.3
De-Emphasis Filter
The CS4270 includes on-chip digital de-emphasis. Figure 11 shows the de-emphasis curve for Fs equal to 44.1 kHz. The frequency response of the de-emphasis curve will scale proportionally with changes in sample rate, Fs. Please see Section 5.1.7 for the desired de-emphasis control for Stand-Alone mode and Section 5.2.8 for control port mode. The de-emphasis feature is included to accommodate audio recordings that utilize 50/15 s pre-emphasis equalization as a means of noise reduction. De-emphasis is only available in Single-Speed Mode.
Gain dB T1=50 s 0dB
T2 = 15 s
-10dB
F1 3.183 kHz
F2 Frequency 10.61 kHz
Figure 11. De-Emphasis Curve
DS686A1
27
CS4270
5.4 Analog Connections
5.4.1 Input Connections
The analog modulator samples the input at 6.144 MHz.The digital filter will reject signals within the stopband of the filter. However, there is no rejection for input signals which are multiples of the input sampling frequency (n x 6.144 MHz), where n=0,1,2,... Refer to Figure 12 which shows the recommended topology of the analog input network. The capacitor values chosen not only provide the appropriate filtering of noise at the modulator sampling frequency, but also act as a charge source for the internal sampling circuits. The use of capacitors which have a large voltage coefficient (such as general purpose ceramics) must be avoided since these can degrade signal linearity.
Analog Input R1 R2 2200 pF 10 F
AINx
CS4270
Figure 12. CS4270 Recommended Analog Input Network
Three parameters determine the values of resistors R1 and R2 as shown in Figure 12: source impedance, attenuation, and input impedance. Source impedance is defined as the impedance as seen from the ADC looking back into the signal network. Analog performance is optimized for small source impedance and a source impedance above 2.5 k results in degraded THD+N. The required attenuation factor depends on the magnitude of the input signal. The full-scale input voltage scales with VA; for VA = 5 V, the CS5344 full-scale input magnitude is 1 Vrms. R1 and R2 should be set such that an input signal greater than the full-scale input should be attenuated to the appropriate magnitude. Typical line-level voltage in audio applications is 2 Vrms, in which case R1 and R2 must combine to form an attenuation factor of 2, thus giving the CS5344 a 1 Vrms input. Input impedance is the impedance from the signal source to the ADC analog input pins. The target input impedance depends on the overall system specifications, but typical audio systems require an input impedance of 10 k. Table 6 shows the input parameters and the associated design equations. Figure 13 illustrates an example configuration for a source impedance of 46 , an attenuation factor of 1, and input impedance of 9.8 k. Source Impedance ( R1 x R2 )
-----------------------R1 + R2
Attenuation Factor
R2 ------------------R1 x R2 ( R1 + R2 )
Input Impedance
Table 6. Analog Input Design Parameters
28
DS686A1
CS4270
Analog Input 47 10 F
AINx
9.76 k
2200 pF
CS4270
Figure 13. CS5344 Example Analog Input Network
5.4.2 Output Connections
The analog output filter present in the CS4270 is a switched-capacitor filter followed by a continuous time low pass filter. Its response, combined with that of the digital interpolator, is given in Figures Figures 19 42. The recommended external analog circuitry is shown in Figure 14.
3.3F AOUTx
470 Analog Output
+
10k C R ext
CS4270
R ext C= + 470 470 ) 4 Fs ( Rext For best 20 kHz response
Figure 14. CS4270 Recommended Analog Output Filter
5.5
Mute Control
The Mute Control pins become active during power-up initialization, reset, muting, when the MCLK to LRCK ratio is incorrect, and during power-down. The MUTE pins are intended to be used as control for an external mute circuit in order to add off-chip mute capability. The CS4270 also features Auto-Mute, which is enabled by default. The Auto-Mute function causes the MUTE pin corresponding to an individual channel to activate following the reception of 8192 consecutive static-level audio samples on the respective channel. A single transition of data on the channel will cause the corresponding MUTE pin to deactivate. Use of the Mute Control function is not mandatory but recommended for designs requiring the absolute minimum in extraneous clicks and pops. Also, use of the Mute Control function can enable the system
DS686A1
29
CS4270
designer to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute circuit. The MUTE pins are active-low. See Figure 15 for a suggested active-low mute circuit.
+V EE AC Couple AOUTx LPF
560
Audio Out 47 k
-V EE CS4270 +V A MMUN2111LT1 MUTEx 2 k
10 k
-V EE
Figure 15. Suggested Active-Low Mute Circuit
5.6
Synchronization of Multiple Devices
In systems where multiple ADCs are required, care must be taken to achieve simultaneous sampling. To ensure synchronous sampling, the MCLK and LRCK must be the same for all of the CS4270's in the system. If only one MCLK source is needed, one solution is to place one CS4270 in Master Mode, and slave all of the other CS4270's to the one master. If multiple MCLK sources are needed, a possible solution would be to supply all clocks from the same external source and time the CS4270 reset with the inactive edge of MCLK. This will ensure that all converters begin sampling on the same clock edge.
5.7
Grounding and Power Supply Decoupling
As with any high resolution converter, the CS4270 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. Figure 10 shows the recommended power arrangements, with VA and VD connected to clean supplies. VD, which powers the digital filter, may be run from the system digital supply (VD) or may be powered from the analog supply (VA) via a resistor. In this case, no additional devices should be powered from VD. Power supply decoupling capacitors should be as near to the CS4270 as possible, with the low value ceramic capacitor being the nearest. All signals, especially clocks, should be kept away from the VREF and VCOM pins in order to avoid unwanted coupling into the modulators. The VREF and VCOM decoupling capacitors, particularly the 0.1 F, must be positioned to minimize the electrical path from VREF and AGND. The CDB4270 evaluation board demonstrates the optimum layout and power supply arrangements. To minimize digital noise, connect the CS4270 digital outputs only to CMOS inputs.
30
DS686A1
CS4270 6. CONTROL PORT INTERFACE
The Control Port is used to load all the internal settings of the CS4270. The operation of the Control Port may be completely asynchronous to the audio sample rate. However, to avoid potential interference problems, the Control Port pins should remain static if no operation is required. The Control Port has 2 modes: SPI and IC, with the CS4270 operating as a slave to control messages in both modes. If IC operation is desired, AD0/CS should be tied to VLC or DGND. If the CS4270 ever detects a high to low transition on AD0/CS after power-up, SPI mode will be selected. Upon release of the RST pin, the CS4270 will wait approximately 10 ms before it begins its start-up sequence. The part defaults to Stand-Alone Mode, in which all operational modes are controlled as described in Section 5.1 on page 22. If the user initiates communication to the part through the SPI or IC interface, the part enters Control-Port Mode and all operational modes are controlled by the Control Port registers. If system requirements do not allow writing to the control port immediately following the release of RST, the SDIN line should be held at logic "0" until the proper serial mode can be selected.
6.1
SPITM Mode
In SPI mode, CS is the CS4270 chip select signal, CCLK is the control port bit clock, CDIN is the input data line from the microcontroller and the chip address is 1001111. All control signals are inputs and data is clocked in on the rising edge of CCLK. Figure 16 shows the operation of the Control Port in SPI mode. To write to a register, bring CS low. The first 7 bits on CDIN form the chip address, and must be 1001111. The eighth bit is a read/write indicator (R/W), which must be low to write. The next 8 bits form the Memory Address Pointer (MAP), which is set to the address of the register that is to be updated. The next 8 bits are the data which will be placed into the register designated by the MAP. See Table 9 on page 35.
CS CCLK CHIP ADDRESS CDIN
1001111
R/W
MAP
MSB
DATA
LSB
byte 1 MAP = Memory Address Pointer
byte n
Figure 16. Control Port Timing, SPI mode
The CS4270 has MAP auto increment capability, enabled by the INCR bit in the MAP. If INCR is 0, then the MAP will stay constant for successive writes. If INCR is set, then MAP will auto increment after each byte is written, allowing block writes to successive registers.
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31
CS4270
6.2 IC Mode
In IC mode, SDA is a bi-directional data line. Data is clocked into and out of the part by the clock, SCL, with the clock to data relationship as shown in Figure 17. There is no CS pin. Pins AD0, AD1, and AD2 form the partial chip address and should be tied to VLC or DGND as required. The upper 4 bits of the 7-bit address field must be 1001. To communicate with the CS4270, the three lower bits of the chip address field should match the setting on the AD0, AD1, and AD2 pins. The eighth bit of the address byte is the R/W bit (high for a read, low for a write). The next byte is the Memory Address Pointer, MAP, which selects the register to be read or written. If the operation is a write, the MAP is then followed by the data to be written. If the operation is a read, then the contents of the register pointed to by the MAP will be output after the chip address. The CS4270 has MAP auto increment capability, enabled by the INCR bit in the MAP. If INCR is 0, then the MAP will stay constant for successive writes. If INCR is set, then MAP will auto increment after each byte is written, allowing block reads or writes of successive registers.
Note 1 SDA
1001 ADDR AD2 - AD0 R/W ACK DATA 1-8 ACK DATA 1-8 ACK
SCL Start Stop
Note: If operation is a write, this byte contains the Memory Address Pointer, MAP.
Figure 17. Control Port Timing, IC Mode
7 INCR 0
6 Reserved 0
5 Reserved 0
4 3 Reserved MAP3 0 0 INCR - Auto MAP Increment Enable Default = `0'. 0 - Disabled 1 - Enabled
2 MAP2 0
1 MAP1 0
0 MAP0 0
MAP(3:0) - Memory Address Pointer Default = `0000'.
Table 7. Memory Address Pointer
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DS686A1
CS4270 7. REGISTER QUICK REFERENCE
This table shows the register names and their associated default values. Addr Function 7
id<3> 1
6
id<2> 1
5
id<1> 0
4
id<0> 0 Reserved 0
3
rev<3> 0 Reserved 0 MCLK freq<2> 0 DAC_DIF0 0
2
rev<2> 0 Reserved 0 MCLK freq<1> 0 Reserved 0
1
rev<1> 0 PDN_DAC 0 MCLK freq<0> 0 Reserved 0 Invert DAC ch A 0 Mute DAC ch B
0
rev<0> 1 PDN 0 PopGuard Disable 0 ADC_DIF0 0 De-Emph 0 Mute DAC ch A
01h ID 02h Power
Control
Freeze 0
Reserved PDN_ADC 0 0
03h Funct Mode
Reserved Reserved 0 Freeze A 0 0 Freeze B 0 soft_dac 1
FM_&_M/S FM_&_M/S_ _Mode1 Mode0 1 Digital Loopback 0 zc_dac 1 1 DAC_DIF1 0 Invert ADC ch B 0 Mute ADC SP ch B
04h Serial Format ADC HPF ADC HPF
05h Transition
Control
DAC Single Vol 0
Invert ADC Invert DAC ch A ch B 0 Mute ADC SP ch A 0 Mute Polarity
06h Mute
Reserved Reserved Auto Mute
0 07h Vol Ctrl
AOUTA dacA vol<7>
0
dacA vol<6>
1
dacA vol<5>
0
dacA vol<4>
0
dacA vol<3>
0
dacA vol<2>
0
dacA vol<1>
0
dacA vol<0>
0 08h Vol Ctrl
AOUTB dacB vol<7>
0
dacB vol<6>
0
dacB vol<5>
0
dacB vol<4>
0
dacB vol<3>
0
dacB vol<2>
0
dacB vol<1>
0
dacB vol<0>
0
0
0
0
0
0
0
0
DS686A1
33
CS4270 8. REGISTER DESCRIPTION
** All registers are read/write in IC mode and SPI mode, unless otherwise noted**
8.1
Chip ID - Address 01h
7 id<3> 6 id<2> 5 id<1> 4 id<0> 3 rev<3> 2 rev<2> 1 rev<1> 0 rev<0>
Function: This register is Read-Only. Bits 7 through 4 are the part number ID which is 1100b (01h) and the remaining bits (b3:b0) are for the chip revision.
8.2
Power Control - Address 02h
7 Freeze 6 Reserved 5 PDN_ADC 4 Reserved 3 Reserved 2 Reserved 1 PDN_DAC 0 PDN
8.2.1 Freeze (Bit 7)
Function: This function allows modifications to be made to certain control port bits without the changes taking effect until the Freeze bit is disabled. To make multiple changes to these bits take effect simultaneously, set the Freeze bit, make all changes, then clear the Freeze bit. The bits affected by the Freeze function are listed below: - - - - Register 05h (Bits 7:0) Register 06h (Bits 7:0) Register 07h (Bits 7:0) Register 08h (Bits 7:0)
8.2.2 PDN_ADC (Bit 5)
Function: The ADC portion of the device will enter a low-power state whenever this bit is set.
8.2.3 PDN_DAC (Bit 1)
Function: The DAC portion of the device will enter a low-power state whenever this bit is set.
8.2.4 Power Down (Bit 0)
Function: The device will enter a low-power state whenever this bit is set. The contents of the control registers are retained when the device is in power-down.
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CS4270
8.3
7 Reserved
Mode Control - Address 03h
6 Reserved 5 FM_&_M/S_ Mode1 4 3 2 1 FM_&_M/S_ MCLK freq<2> MCLK freq<1> MCLK freq<0> Mode0 0 PopGuard Disable
8.3.1 ADC Functional Mode & Master / Slave Mode (Bits 5:4)
Function: In Control Port Master Mode, the user must configure the CS4270 Speed Mode with these bits. In Control Port Slave Mode, the CS4270 auto-detects speed mode.
FM_&_M/S_ FM_&_M/S_ Mode1 Mode0
Mode
Single-Speed Mode: 4 to 54 kHz sample rates Double-Speed Mode: 50 to 108 kHz sample rates Quad-Speed Mode: 100 to 216 kHz sample rates Slave Mode (default) Table 8. Functional Mode Selection
0 0 1 1
0 1 0 1
8.3.2 Ratio Select (Bits 3:1)
Function: These bits are used to select the clocking ratios. MCLK freq<2> 0 0 0 0 1 MCLK freq<1> 0 0 1 1 0 MCLK freq<0> 0 1 0 1 0 Mode
Divide by 1 (default) Divide by 1.5 Divide by 2 Divide by 3 Divide by 4
Table 9. MCLK Divider Configuration
8.3.3 PopGuard Disable (Bit 0)
Function: Disables PopGuard when set. PopGuard is enabled by default.
8.4
ADC and DAC Control - Address 04h
6 ADC HPF Freeze B 5 Digital Loopback 4 DAC_DIF1 3 DAC_DIF0 2 Reserved 1 Reserved 0 ADC_DIF0
7 ADC HPF Freeze A
8.4.1 ADC HPF Freeze A (Bit 7)
Function: When this bit is set, the internal high-pass filter for the selected channel will be disabled.The current DC offset value will be frozen and continuously subtracted from the conversion result. Section 5.2.7 "HighPass Filter and DC Offset Calibration" on page 26. DS686A1 35
CS4270
8.4.2 ADC HPF Freeze B (Bit 6)
Function: When this bit is set, the internal high-pass filter for the selected channel will be disabled.The current DC offset value will be frozen and continuously subtracted from the conversion result. Section 5.2.7 "HighPass Filter and DC Offset Calibration" on page 26.
8.4.3 Digital Loopback (Bit 5)
Function: When this bit is set, an internal digital loopback from the ADC to the DAC will be enabled. Please refer to Section 5.2.5 "Internal Digital Loopback" on page 26.
8.4.4 DAC Digital Interface Format (Bits 4:3)
Function: The DAC Digital Interface Format and the options are detailed in Table 10 and Figures 5 through 7. DAC_DIF1 DAC_DIF0 0 0 0 1 1 0 1 1 Description Left Justified, up to 24-bit data (default) IS, up to 24-bit data Right Justified, 16-bit Data Right Justified, 24-bit Data
Table 10. DAC Digital Interface Formats
Format 0 1 2 3
Figure 5 6 7 7
8.4.5 ADC Digital Interface Format (Bit 0)
Function: The required relationship between LRCK, SCLK and SDOUT for the ADC is defined by the ADC Digital Interface Format. The options are detailed in Table 11 and may be seen in Figures 5 and 6. ADC_DIF 0 1 Description Left Justified, up to 24-bit data (default) IS, up to 24-bit data
Table 11. ADC Digital Interface Formats
Format 0 1
Figure 5 6
36
DS686A1
CS4270
8.5 Transition Control - Address 05h
6 soft_dac 5 zc_dac 4 invert ADC ch B 3 invert ADC ch A 2 invert DAC ch B 1 invert DAC ch A 0 De-emph 7 DAC Single Volume
8.5.1 DAC Single Volume (Bit 7)
Function: The AOUTA and AOUTB volume levels are independently controlled by the A and the B Channel Volume Control Bytes when this function is disabled. The volume on both AOUTA and AOUTB are determined by the A Channel Volume Control Byte (07h) and the B Channel Byte (08h) is ignored when this function is enabled. Volume and muting functions are affected by the Soft Ramp and ZeroCross functions below.
8.5.2 Soft Ramp or Zero Cross Enable (Bits 6:5)
Function: Soft Ramp Enable Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods. See Table 12 on page 37. Zero Cross Enable Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. See Table 9 on page 35. Soft Ramp and Zero Cross Enable Soft Ramp and Zero Cross Enable dictate that signal level changes, either by attenuation changes or muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. See Table 9 on page 35. Soft ZeroCross Mode 0 0 Changes to affect immediately 0 1 Zero Cross enabled 1 0 Soft Ramp enabled 1 1 Soft Ramp and Zero Cross enabled (default)
Table 12. Soft Cross or Zero Cross Mode Selection
8.5.3 Invert Signal Polarity (Bits 4:1)
Function: When set, this bit activates an inversion of the signal polarity for the appropriate channel. This is useful if a board layout error has occurred or in other situations where a 180 degree phase shift is desirable.
DS686A1
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CS4270
8.5.4 De-Emphasis Control (Bit 0)
Function: Implementation of the standard 50/15 s digital de-emphasis filter on the DAC output requires reconfiguration of the digital filter to maintain the proper filter response for 44.1 kHz sample rate. Figure 18 shows the filter response. NOTE: De-emphasis is available only in Single-Speed Mode.
Gain dB T1=50 s 0dB
T2 = 15 s
-10dB
F1 3.183 kHz
F2 Frequency 10.61 kHz
Figure 18. De-Emphasis Curve
8.6
7
Mute Control - Address 06h
6 5 Auto Mute 4 3 Mute ADC SP Mute ADC SP ch B ch A 2 mute polarity 1 0 Mute DAC SP Mute DAC SP ch B ch B
8.6.1 Auto-Mute (Bit 5)
Function: When set, enables the Auto-Mute function. Section 5.2.6 "Auto-Mute" on page 26.
8.6.2 ADC Channel A & B Mute (Bits 4:3)
Function: When this bit is set, the output of the ADC for the selected channel will be muted.
8.6.3 Mute Polarity (Bit 2)
Function: The MUTEA and MUTEB pins (pins 24 and 21) are active low by default. When this bit is set, these pins are active high.
8.6.4 DAC Channel A & B Mute (Bits 1:0)
Function: When this bit is set, the output of the DAC for the selected channel will be muted.
38
DS686A1
CS4270
8.7 DAC Channel A Volume Control - Address 07h
7 dacA vol<7> 6 dacA vol<6> 5 dacA vol<5> 4 dacA vol<4> 3 dacA vol<3> 2 dacA vol<2> 1 dacA vol<1> 0 dacA vol<0>
Function: See Section 8.8 DAC Channel B Volume Control - Address 08h.
8.8
DAC Channel B Volume Control - Address 08h
7 dacB vol<7> 6 dacB vol<6> 5 dacB vol<5> 4 dacB vol<4> 3 dacB vol<3> 2 dacB vol<2> 1 dacB vol<1> 0 dacB vol<0>
Function: The digital volume control allows the user to attenuate the signal in 0.5 dB increments from 0 to -127 dB. The vol<0> bit activates a 0.5 dB attenuation when set, and no attenuation when cleared. The Vol[7:1] bits activate attenuation equal to their decimal value (in dB). Example volume settings are decoded as shown in Table 13. The volume changes are implemented as dictated by the DACSoft and DACZeroCross bits in the Transition Control register (see Section 8.5.2). Binary Code 00000000 00000001 00101000 00101001 11111110 11111111 Volume Setting 0 dB -0.5 dB -20 dB -20.5 dB -127 dB -127.5 dB
Table 13. Digital Volume Control
DS686A1
39
CS4270
9. PARAMETER DEFINITIONS
Dynamic Range The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale. This technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels. Total Harmonic Distortion + Noise The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured at -1 and -20 dBFS as suggested in AES17-1991 Annex A. Frequency Response A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at 1 kHz. Units in decibels. Interchannel Isolation A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with no signal to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Error The deviation from the nominal full-scale analog output for a full-scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/C. Offset Error The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV.
40
DS686A1
CS4270 10.PACKAGE DIMENSIONS 24L TSSOP (4.4 mm BODY) PACKAGE DRAWING
N
D
E11 A2 A1
L
E
A
e b2 SIDE VIEW
123
END VIEW
SEATING PLANE
TOP VIEW
DIM A A1 A2 b D E E1 e L
MIN -0.002 0.03150 0.00748 0.378 BSC 0.248 0.169 -0.020 0
INCHES NOM -0.004 0.035 0.0096 0.382 BSC 0.2519 0.1732 0.026 BSC 0.024 4
MAX 0.47 0.006 0.04 0.012 0.386 BSC 0.256 0.177 -0.029 8
MIN -0.05 0.80 0.19 9.60 BSC 6.30 4.30 -0.50 0
MILLIMETERS NOM -0.10 0.90 0.245 9.70 BSC 6.40 4.40 0.65 BSC 0.60 4
NOTE MAX 1.20 0.15 1.00 0.30 9.80 BSC 6.50 4.50 -0.75 8
2,3 1 1
JEDEC #: MO-153 Controlling Dimension is Millimeters. Notes: 1. "D" and "E1" are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. Dimension "b" does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of "b" dimension at maximum material condition. Dambar intrusion shall not reduce dimension "b" by more than 0.07 mm at least material condition. 3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
DS686A1
41
CS4270 11.APPENDIX
0
0
20
20
Amplitude (dB)
Amplitude (dB)
40
40
60
60
80
80
100
100
120
120
0.4
0.5
0.6 0.7 0.8 Frequency(normalized to Fs)
0.9
1
0.4
0.42
0.44
0.46
0.48 0.5 0.52 Frequency(normalized to Fs)
0.54
0.56
0.58
0.6
Figure 19. DAC Single-Speed (fast) Stopband Rejection
0
Figure 20. DAC Single-Speed (fast) Transition Band
0.02
1
0.015
2
0.01
3
0.005 Amplitude (dB)
Amplitude (dB)
4
5
0
6
0.005
7
0.01
8
0.015
9
10 0.45
0.46
0.47
0.48
0.49 0.5 0.51 Frequency(normalized to Fs)
0.52
0.53
0.54
0.55
0.02
0
0.05
0.1
0.15
0.2 0.25 0.3 Frequency(normalized to Fs)
0.35
0.4
0.45
0.5
Figure 21. DAC Single-Speed (fast) Transition Band (detail)
Figure 22. DAC Single-Speed (fast) Passband Ripple
0
0
20
20
Amplitude (dB)
40
60
Amplitude (dB)
0.4 0.5 0.6 0.7 0.8 Frequency(normalized to Fs) 0.9 1
40
60
80
80
100
100
120
120
0.4
0.42
0.44
0.46
0.48 0.5 0.52 Frequency(normalized to Fs)
0.54
0.56
0.58
0.6
Figure 23. DAC Single-Speed (slow) Stopband Rejection
Figure 24. DAC Single-Speed (slow) Transition Band
42
DS686A1
CS4270
0
0.02
1
0.015
2
0.01
3
0.005
Amplitude (dB)
Amplitude (dB)
4
5
0
6
0.005
7
0.01
8
0.015
9
10 0.45
0.02
0.46 0.47 0.48 0.49 0.5 0.51 Frequency(normalized to Fs) 0.52 0.53 0.54 0.55
0
0.05
0.1
0.15
0.2 0.25 0.3 Frequency(normalized to Fs)
0.35
0.4
0.45
0.5
Figure 25. DAC Single-Speed (slow) Transition Band (detail)
Figure 26. DAC Single-Speed (slow) Passband Ripple
0
0
20
20
Amplitude (dB)
Amplitude (dB)
40
40
60
60
80
80
100
100
120
120
0.4
0.5
0.6 0.7 0.8 Frequency(normalized to Fs)
0.9
1
0.4
0.42
0.44
0.46
0.48 0.5 0.52 Frequency(normalized to Fs)
0.54
0.56
0.58
0.6
Figure 27. DAC Double-Speed (fast) Stopband Rejection
0
Figure 28. DAC Double-Speed (fast) Transition Band
0.02
1
0.015
2
0.01
3
Amplitude (dB)
5
Amplitude (dB)
4
0.005
0
6
0.005
7
0.01
8
9
0.015
10 0.45
0.46
0.47
0.48
0.49 0.5 0.51 Frequency(normalized to Fs)
0.52
0.53
0.54
0.55
0.02
0
0.05
0.1
0.15
0.2 0.25 0.3 Frequency(normalized to Fs)
0.35
0.4
0.45
0.5
Figure 29. DAC Double-Speed (fast) Transition Band (detail)
Figure 30. DAC Double-Speed (fast) Passband Ripple
DS686A1
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CS4270
0
0
20
20
Amplitude (dB)
Amplitude (dB)
40
40
60
60
80
80
100
100
120
120
0.2
0.3
0.4
0.5 0.6 0.7 Frequency(normalized to Fs)
0.8
0.9
1
0.2
0.3
0.4 0.5 0.6 Frequency(normalized to Fs)
0.7
0.8
Figure 31. DAC Double-Speed (slow) Stopband Rejection
Figure 32. DAC Double-Speed (slow) Transition Band
0
0.02
1
0.015
2
0.01
3
0.005 Amplitude (dB)
Amplitude (dB)
4
5
0
6
0.005
7
0.01
8
0.015
9
10 0.45
0.46
0.47
0.48
0.49 0.5 0.51 Frequency(normalized to Fs)
0.52
0.53
0.54
0.55
0.02
0
0.05
0.1
0.15 0.2 Frequency(normalized to Fs)
0.25
0.3
0.35
Figure 33. DAC Double-Speed (slow) Transition Band (detail)
Figure 34. DAC Double-Speed (slow) Passband Ripple
0
0
20
20
40 Amplitude (dB)
Amplitude (dB)
40
60
60
80
80
100
100
120
120
0.2
0.3
0.4
0.5 0.6 0.7 Frequency(normalized to Fs)
0.8
0.9
1
0.2
0.3
0.4 0.5 0.6 Frequency(normalized to Fs)
0.7
0.8
Figure 35. DAC Quad-Speed (fast) Stopband Rejection
Figure 36. DAC Quad-Speed (fast) Transition Band
44
DS686A1
CS4270
0
0.2
1
0.15
2
0.1
3
0.05
Amplitude (dB)
Amplitude (dB) 0.05 0.1 0.15 0.2
4
5
0
6
7
8
9
10 0.45
0.46
0.47
0.48
0.49 0.5 0.51 Frequency(normalized to Fs)
0.52
0.53
0.54
0.55
0
0.05
0.1 0.15 Frequency(normalized to Fs)
0.2
0.25
Figure 37. DAC Quad-Speed (fast) Transition Band (detail)
Figure 38. DAC Quad-Speed (fast) Passband Ripple
0
0
20
20
Amplitude (dB)
Amplitude (dB)
40
40
60
60
80
80
100
100
120
120
0.1
0.2
0.3
0.4 0.5 0.6 0.7 Frequency(normalized to Fs)
0.8
0.9
1
0.1
0.2
0.3
0.4 0.5 0.6 Frequency(normalized to Fs)
0.7
0.8
0.9
Figure 39. DAC Quad-Speed (slow) Stopband Rejection
0
Figure 40. DAC Quad-Speed (slow) Transition Band
0.02
1
0.015
2
0.01
3
0.005 Amplitude (dB)
Amplitude (dB)
4
5
0
6
0.005
7
0.01
8
0.015
9
10 0.45
0.46
0.47
0.48
0.49 0.5 0.51 Frequency(normalized to Fs)
0.52
0.53
0.54
0.55
0.02
0
0.02
0.04 0.06 0.08 Frequency(normalized to Fs)
0.1
0.12
Figure 41. DAC Quad-Speed (slow) Transition Band (detail)
Figure 42. DAC Quad-Speed (slow) Passband Ripple
DS686A1
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CS4270
0 -10 -20 -30 -40 -50 Amplitude (dB) -60 -70 -80 -90 -100 -110 -120 -130 -140 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency (normalized to Fs)
0 -10 -20 -30 -40 -50 Amplitude (dB) -60 -70 -80 -90 -100 -110 -120 -130 -140 0.40
0.42
0.44
0.46
0.48
0.50
0.52
0.54
0.56
0.58
0.60
Frequency (normalized to Fs)
Figure 43. ADC Single-Speed Mode Stopband Rejection
Figure 44. ADC Single-Speed Mode Transition Band
0
0.10
-1
0.08
-2
0.05
-3
Amplitude (dB)
-5
Amplitude (dB)
0.46 0.47 0.48 0.49 0.50 0.51 0.52 0.53 0.54 0.55
-4
0.03
0.00
-6
-0.03
-7
-0.05
-8
-9
-0.08
-10 0.45
Frequency (normalized to Fs)
-0.10 0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
Frequency (normalized to Fs)
Figure 45. ADC Single-Speed Mode Transition Band (Detail)
Figure 46. ADC Single-Speed Mode Passband Ripple
0 -10 -20 -30 -40 -50 Amplitude (dB)
0 -10 -20 -30 -40 -50 Amplitude (dB) -60 -70 -80 -90 -100 -110 -120 -130 -140 0.40
-60 -70 -80 -90 -100 -110 -120 -130 -140 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency (normalized to Fs)
0.43
0.45
0.48
0.50
0.53
0.55
0.58
0.60
0.63
0.65
0.68
0.70
Frequency (normalized to Fs)
Figure 47. ADC Double-Speed Mode Stopband Rejection
Figure 48. ADC Double-Speed Mode Transition Band
46
DS686A1
CS4270
0
0.10
-1
0.08
-2
0.05
-3
Amplitude (dB)
-5
Amplitude (dB)
0.43 0.45 0.48 Frequency (normalized to Fs) 0.50 0.53 0.55
-4
0.03
0.00
-6
-0.03
-7
-8
-0.05
-9
-0.08
-10 0.40
-0.10 0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
Frequency (normalized to Fs)
Figure 49. ADC Double-Speed Mode Transition Band (Detail)
0 -10 -20 -30 -40 Amplitude (dB) -50 -60 -70 -80
-90 Amplitude (dB) 0 -10 -20 -30 -40 -50 -60 -70 -80
Figure 50. ADC Double-Speed Mode Passband Ripple
-90 -100 -110 -120 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency (normalized to Fs)
-100 -110 -120 -130 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 Frequency (normalized to Fs)
Figure 51. ADC Quad-Speed Mode Stopband Rejection
0
Figure 52. ADC Quad-Speed Mode Transition Band
0.10
-1
0.08
-2
0.06
-3
0.04
Amplitude (dB)
-5
Amplitude (dB)
0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6
-4
0.02
0.00
-6
-0.02
-7
-0.04
-8
-0.06
-9
-0.08
-10 Frequency (normalized to Fs)
-0.10 0.00
0.05
0.10
0.15
0.20
0.25
Frequency (normalized to Fs)
Figure 53. ADC Quad-Speed Mode Transition Band (Detail)
Figure 54. ADC Quad-Speed Mode Passband Ripple
DS686A1
47
CS4270 12.REVISION HISTORY
Release A1 Date May 2005 Initial Advance Release Changes
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com IMPORTANT NOTICE
"Advance" product information describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. SPI is a trademark of Motorola, Inc.
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Price & Availability of CS4270-DZZR

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